• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    A method of stressing a channel region of a semiconductor-on-insulator type transistor by means of a constraint storage technique SMT in which, before making the gate of the transistor, regions are amorphized under the insulating layer of the substrate (Figure 6).
    公开号:FR3023411A1
    申请号:FR1456521
    申请日:2014-07-07
    公开日:2016-01-08
    发明作者:Shay Reboh；Laurent Grenouillet；Royer Cyrille Le；Sylvain Maitrejean；Yves Morand
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART This description relates to the field of transistor structures formed on a semiconductor-on-insulator substrate, and more particularly to those having a channel zone undergoing deformation. BACKGROUND OF THE INVENTION or mechanical stress. By mechanical deformation is meant a material which has its parameter (s) elongated crystal (s) or shortened (s). In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of a crystalline material, it is said to be in tension strain. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be compressive deformation or compression. To these states of mechanical deformation, one associates states of mechanical stresses. However, it is also common to refer to these deformation states as mechanical stress states. In the remainder of the present application, this notion of strain ("strain" in the English terminology) will be generically referred to as "constraint". A stress applied to a semiconductor material induces a modification of the crystal lattice and thus of its band structure, which will result in a modification of the mobility of the carriers in this material. The mobility of the electrons is increased (respectively diminished) by a stress in tension (respectively in compression) of the semiconductor material in which they transit while the mobility of the holes will be increased (respectively decreased) when the semiconductor is in compression (respectively in voltage). To generate a constraint in the channel of a transistor, a so-called constraint memorization technique (SMT) has been developed.
    [0002] It consists first of all in carrying out amorphization by ion implantation of the semiconductor material of source 1 and drain 2 zones of a transistor T (FIG. 1A). Then, a straining layer 8 is deposited, based on a material having an intrinsic mechanical stress such as silicon nitride (SixNy) on the source and drain zones and so as to cover the gate 4 of the transistor , and in particular its side faces on which insulating spacers 5 are provided. Then, recrystallization annealing of the source 1 and drain 2 zones is performed (FIG. 1B). During this recrystallization annealing of the dislocations 9 in the semiconductor material related in particular to the meeting of different recrystallization fronts are generated at the source and drain zones. These dislocations induce a mechanical stress in the material capable of propagating up to the channel zone 3. The stress exerted on the channel is memorized during this annealing. Then (Figure 1C), the stressing layer 8 can be removed. Such a method is evoked for example in the document: "Molecular Dynamic Simulation Study of Stress Memorization in Si Dislocations", Shen et al. IEEE 2012, or in the "Novel Stress Memorization Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k / Metal Gate Devices", by Lim et al. IEEE 2010, or in the document "Strain mapping of Si devices with stress memorization processing" by Wang et al. Applied Physics Letters 103 (2013). The use of a SMT-type method for stressing a channel region of a transistor formed in the surface layer of a semiconductor-on-insulator substrate poses a problem, in particular because of the generally low thickness. of this layer. The document US 2011 / 029110A1 provides a solution to this problem by proposing a method using a stress storage technique SMT, in which the dislocations are formed in the support layer of an SOI substrate located under the so-called insulating layer of BOX. .
    [0003] This technique is implemented after having made the gate of the transistor on the substrate. Thus, after having formed the gate of the transistor, regions of the support layer located on either side of the gate are implanted in alignment with the source and drain zones. Then, a strain layer is deposited on the grid. The amorphized regions of the support layer which are not located opposite the gate of the transistor are then recrystallized. This method has the disadvantage that the extent of the amorphized zone necessarily depends on the dimensions of the gate, which can be problematic in particular for transistors having significant gate lengths. In this case, it may indeed be difficult or impossible to impose a constraint in the center of the channel region of the transistor. There is the problem of finding a new method for producing a constrained channel transistor on a semiconductor-on-insulator substrate, which does not have the disadvantages mentioned above. PRESENTATION OF THE INVENTION The present invention relates first of all to a method for producing a transistor device and in particular to a method for constraining a channel region of a transistor on a semiconductor-on-insulator type substrate comprising a support layer, a superficial semiconductor layer, and an insulating layer separating the support layer and the surface layer. The present invention thus provides a method comprising the following steps: forming a masking on a first zone of the surface layer of the substrate in which a channel zone of a transistor is intended to be made, rendering amorphous at least a first a region of the support layer located directly above an area of the surface layer which is not protected by masking and which abuts a second region of the support layer directly above the masking; re-crystallizing the first region of the support layer so that during this recrystallization a mechanical stress is applied to the substrate through a stress layer formed on the substrate, and after removing the masking and the stress layer: forming on the first zone of the surface layer in which a channel zone of a transistor is intended to be produced, a grid for the transistor. Thus, dislocations are produced in the support layer to induce mechanical stress in the surface layer and in particular in an area in which a channel of the transistor is to be realized. These dislocations are formed before making the grid. The extent of the area in which the dislocations are made is thus not necessarily related to the dimensions of the grid.
    [0004] A better constraint of the channel area can thus be obtained, even for grids of large dimensions. According to one possible embodiment, the stress layer may be a layer having an intrinsic stress, and is deposited after forming the masking and prior to recrystallization.
    [0005] According to an alternative embodiment, the masking may be based on a constrained material and form the stress layer during the recrystallization step. According to one possibility of implementing the method, the masking can be formed of a plurality of distinct masking blocks.
    [0006] The distribution of the masking blocks is adapted according to the desired density of dislocations. The masking may comprise at least one opening disposed between two masking blocks and revealing the first zone in which a channel of a transistor is intended to be produced.
    [0007] Thus, dislocations can be made in the support layer closer to the channel zone, so as to further constrain the latter. The masking may comprise one or more openings between the masking blocks at least one opening of the masking revealing a first zone of the surface layer, in which or on which a source or drain zone of the transistor is made or intended to be made. According to one possibility of implementing the method, the masking may be formed of a network of parallel masking blocks, the masking having openings also arranged in an array of parallel openings.
    [0008] The orientation of the masking blocks and openings may be provided depending on the direction in which the current of the transistor is to flow. This orientation can be advantageously provided orthogonal to the direction in which a current is intended to flow in the channel zone. According to a possibility of implementing the method, the surface layer may be provided based on a material that has an intrinsic stress, the substrate being a semiconductor substrate constrained on insulator. In this case, the mechanical stress exerted by the stress layer may be provided opposite to that intrinsic of the semiconductor material. With such a method, when the semiconductor material has intrinsic bi-axial stress, by applying a mechanical stress through the stress layer opposite to that of an intrinsic stress component of the semiconductor material, it is possible to to transform the intrinsic biaxial stress of the semiconductor material into a uni-axial stress. For example, if the semiconductor material of the surface layer has a biaxial stress in compression, a voltage stress layer may thus make it possible to improve the performance in terms of current of the transistor. According to one possible implementation, the substrate may be of the type sSiGeO1 ("strained Silicon Germanium On Insulator") having a surface layer of SiGe constrained in biaxial compression, the mechanical stress applied in step c) being able to then be a mechanical stress in tension.
    [0009] According to one possible embodiment of the method, the transistor may advantageously be of the FDSOI type (for "Fully Depleted Silicon On Insulator") or UTBB (UTBB for "Ultra Thin Body and Box"). Thus, the thickness of the superficial semiconductor layer may be less than 25 nm and the thickness of the insulating layer provided less than 25 nm. According to one possible implementation of the method, the surface layer may be based on a III-V material. The present invention also relates to a transistor device (s) obtained using such a method.
    [0010] The present invention further provides a channel-constrained transistor device on a semiconductor-on-insulator-type substrate comprising a semiconductor material-based support layer, a surface semiconductor layer, and an insulating layer separating the semiconductor layer. support and the surface layer, the device comprising dislocations located under the insulating layer and in the semiconductor material of the support layer, the dislocations being arranged facing the channel region of the transistor. These dislocations are provided to induce a constraint in the channel region of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1A-1C illustrate a method of stressing the channel of a transistor according to a technique of stress storage (SMT) according to the prior art; FIGS. 2A-2F illustrate an example of a method for making it possible to constrain a channel of a transistor formed on a semiconductor-on-insulator substrate, in which amorphization dislocations of regions of the support layer of the substrate are formed. through masking then recrystallization while a mechanical stress is applied to the support, these steps being performed prior to the formation of the gate of this transistor; FIGS. 3A-3D, 4 illustrate an alternative method in which the masking is in the form of a plurality of blocks arranged opposite the active zone of the transistor; FIG. 5 illustrates an alternative method in which the masking used during the amorphization step also serves to constrain the substrate during the recrystallization step; FIG. 6 illustrates a variant of the method in which the gate of the transistor is formed opposite several regions made amorphous and then recrystallized from the support layer of the semiconductor-on-insulator substrate; Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
    [0011] The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. In addition, in the description below, terms that depend on the orientation, such as "under", "on", "below", "above", etc. of a structure apply considering that the structure is oriented in the manner illustrated in the figures. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS A first example of a method, in which a stress is applied to a transistor channel resting on a semiconductor-on-insulator substrate, will be described with reference to FIGS. 2A-2D.
    [0012] The starting material of this process is here a semiconductor-on-insulator type substrate, for example of the SOI type (SOI for "silicon on insulator" or "silicon on insulator"). The substrate thus comprises a semiconductor support layer 10, for example Si based, with a thickness (measured in a direction parallel to the z axis of an orthogonal reference [O; x; y; z] given on the FIG. 2A) which can be for example between 40 nm and 750 μm. The substrate further comprises an insulating layer 11, for example based on SiO 2, situated on and in contact with the support layer 10. The insulating layer 11 may for example be BOX (BOX for "Buried Oxide") with a which can be for example between 5 nm and 25 nm. A so-called "superficial" semiconductor layer 12, for example based on Si, is placed on and in contact with said insulating layer 11. This superficial semiconductor layer 12 may have a thickness e2 for example between 3 nm and 25 nm (Figure 2A). At least one masking block 14, for example based on silicon oxide, having a thickness which may for example be between 60 nm and 120 nm, is formed first of all on the surface semiconductor layer 12. thickness range dependent on those of the superficial and insulating layers.
    [0013] This masking block 14 is made facing a first zone 12a of the superficial semiconductor layer 12 in which the channel of the transistor is provided or is intended to be produced. This masking block 14 may have a critical dimension D ("critical dimension" means the smallest dimension of a pattern except its thickness or height), also called width D (measured in a direction parallel to the x axis on Figure 2A) for example between 5 nm and 40 nm. Then (FIG. 2B), a so-called "buried" amorphization of first regions 10b of the support layer 10 located under the insulating layer 11 and in line with second zones 12b of the semiconductor layer 12 which are not protected by masking 14 and adjoin or are contiguous to the first zone 12a of the semiconductor layer 12 superficial. Source and drain regions of the transistor may be provided in and on the second zones 12b. The first regions 10b may be contiguous to the insulating layer 11 under which they are located. The amorphization is carried out so that a second region 10a adjacent the first regions 10b and located opposite the masking and protected by the latter, and a third region 10c located under the first regions 10b retain their crystal structures. The buried amorphization can be carried out using at least one ion implantation step.
    [0014] According to an exemplary embodiment, when the amorphized semiconductor material is Si, the ion implantation of the regions 10b is carried out using species such as Si, Ge, As, P, Ar, for example in a dose of between 1014 and 5.1015cm-2 and with an energy ranging for example between 5 and 50 keV, the dose and the energy chosen depending on the respective thicknesses of the layers 12, 11, 10 in the presence. The height H (measured in a direction parallel to the axis z in FIG. 2B) of regions 10b made amorphous in the support layer may be for example between 40 nm and 90 nm. The depth of the amorphous regions, and in particular that at which there is a point P situated in line with a lateral flank 15 of the masking 14, at the boundary between the first region 10b made amorphous, the second and third regions 10a, 10c, conditions the vertical position of a dislocation that it is desired to generate later in the support layer and consecutively that of the deformation field that will result from this dislocation and that it is desired to impose the superficial semiconductor layer 12 , in particular in its first zone 12a designed to accommodate a transistor channel. The depth of the amorphous regions and the height H depend on the chosen implantation conditions. Next (FIG. 2C), a stressing layer 21 is formed which is also called a "stress layer" intended to induce a given type of stress in the substrate. The stressing layer 21 is deposited in such a way as to cover in particular the lateral flanks 15 of the block 14 and the superficial semiconductor layer 12. This stressing layer 21 may be based on an amorphous material such as, for example, silicon nitride. (SixNy) having an intrinsic elastic stress, for example in tension from 1 GPa to 3 GPa.
    [0015] The regions 10b of the support layer 10 which have been rendered amorphous (Figure 2D) are then recrystallized. For this, at least one thermal annealing is carried out at a temperature which may be for example between 500 ° C. and 1100 ° C. in the case where the insulating layer 11 is based on SiO 2 and the support layer 10 on the basis of Si for the SOI case. The duration of the annealing, adapted as a function of the chosen annealing temperature, can be in this case, for example between 5 s and 1 hour, plus the annealing temperature being high minus a necessary annealing time being important. During recrystallization, recrystallization fronts originating from regions 10a, 10c, the crystal structure of which has been preserved, propagate (the propagation being illustrated by arrows in FIG. 2D) and are intended to meet each other. Recrystallization of the support layer regions 10b generates defects, referred to as dislocations, in the crystalline material that may be produced at the meeting points of the propagation fronts. These dislocations induce a deformation field, and therefore a constraint. The generated stress extends into the surface layer 12 and in particular in the first zone 12a of this layer. At the end of this step, the stress induced by the dislocations is stored.
    [0016] The intensity of the stress experienced by the first zone 12a depends in particular on the choice of the thicknesses e1, ez, of the insulating layer 11 and of the superficial semiconductor layer, of the implantation depth at which the point P is located, as well as the implantation and recrystallization annealing parameters (time, temperature).
    [0017] The shrinkage layer 21 can then be removed. This shrinkage can be carried out for example by etching with the aid of dry etching, for example of the RIE type (for "Reactive Ion Etching") or wet using orthoacoustic acid. -phosphoric hot when the stress layer is based on silicon nitride.
    [0018] Then (FIG. 2E), the masking block 14 is removed. This removal can be carried out for example by etching using HF when the masking is for example based on silicon oxide. Then, in particular, a grid 32 is formed on the first zone 12a of the superficial layer which has been stressed and which is situated opposite the first region 10a of the support layer and between the regions 10b made amorphous and then recrystallized at the same time. previous steps. For this purpose, it is possible to deposit a layer 31 of gate dielectric, for example based on HfO 2, then a gate block 32 on this zone 31. The gate block can be formed of a material such as polysilicon or several stacked materials for example a metallic material such as TiN and a semiconductor material such as polysilicon. Insulating spacers 33, for example based on Si3N4, can then be formed against the lateral flanks of the grid (FIG. 3F).
    [0019] To complete the formation of the transistor, source and drain zones can then be formed (step not shown) using one or more steps of growth of semiconductor material by epitaxy on the zones 12b of the superficial layer. . According to another exemplary embodiment, the density of the dislocations generated in the support layer 10 of the substrate can advantageously be increased by providing amorphous implantation masking in the form of a plurality of distinct parallel blocks 114 spaced apart from one another relative to the first one. zone 12a of the superficial semiconductor layer 12 in which the channel of the transistor is intended to be produced (FIG. 3A).
    [0020] By increasing the density of dislocations generated in the support layer 10, it is thus possible to increase the generated stress field reverberating in the superficial semiconductor layer 12. The masking blocks 114 may have an elongated shape, for example parallelepiped, provided depending on the shape that is desired to give to openings 116 located between these blocks.
    [0021] According to an implementation possibility (FIG. 4 illustrating masking according to a view from above), the masking can be arranged in a network of parallel blocks 114, whose pitch is adapted as a function of the density of regions that one wishes to The orientation of the blocks may further be provided according to the direction in which a current is intended to flow in the channel zone of the transistor. The openings 116 between the masking blocks can then also be arranged in a network of parallel openings. The orientation of the masking blocks 114 so that the latter extend, in the direction of their length (defined in Figures 3A and 4 as a dimension parallel to the y axis), along an axis A'A orthogonal to an axis B'B (corresponding to that in which the length of the channel is measured) through which passes the first zone 12a of the surface layer 12 and indicating the direction in which a current I is intended to flow in the first zone 12a between a source zone and a drain zone of the transistor. In this embodiment, the masking blocks 114 have a critical dimension D1 also called width D1 (measured parallel to the x-axis in FIG. 3A) and a spacing I (corresponding to the critical dimension of the openings 116) such that the sum I + D1 is smaller than the critical dimension of the gate of the transistor to be performed later (see Figure 6). The width or critical dimension D1 may be for example between 15 and 25 nm. The spacing I between the masking blocks 114 may be, for example, 15 and 25 nm. Then "buried" amorphization of regions 10b of the support layer 10 is carried out by implantation through the openings 116 of the masking located between the blocks 114 (FIG. 3B). Several openings 116 of the masking may be located opposite the zone 12a of the surface layer in which a channel of the transistor is provided. Then, the stressing layer 21 is formed by conformal deposition on the masking blocks 14 and on the superficial semiconductor layer 12.
    [0022] In a case for example, where the surface layer 12 is based on a constrained semiconductor material, for example if the starting substrate is of semiconductor type constrained on insulator, the material of the mechanical stress layer can be provided so as to apply a mechanical stress of the opposite type to that of the semiconductor material, for example a voltage stress when the semiconductor material is in biaxial compression. It is thus possible to limit the global stress exerted on the material of the surface layer 12 in a direction of the axis A'A which is orthogonal to that in which a current is intended to flow between the source and the drain and thus to increase the performances of the transistor, in particular when the length of the channel is low, for example less than 1 μm. For example, in a case where the surface layer is based on a semiconductor material such as constrained SiGe having a bi-axial compression stress, for example if the starting substrate is of type sSiGe01 (for "strained SiGe On the "lnstrator"), the stress layer 21 may be based on a stress-strain material such as SixNy. The recrystallization annealing of the regions 10a of the support layer is then carried out using other regions 10a, 10c of this layer whose crystalline structure has been retained as starting regions at recrystallization fronts (FIG. 3C). Stress-inducing dislocations are thus generated in the superficial semiconductor layer 12. The stripping layer 21 and the masking blocks 114 are then removed. Then, a gate dielectric 31 and a gate 32 are formed opposite several regions 10b of the support layer 10 which have been rendered amorphous and then recrystallized (FIG. 3D). Other steps of making insulating spacers, elevated source zone and drain formations can then be performed to complete the formation of the transistor. According to another variant embodiment, the amorphization step can be carried out through openings of a mask 214 that serves both to protect certain areas of the substrate during ion implantation and to apply a mechanical stress on the layers. support 10 and surface 12 of the substrate (Figure 5). This masking 214 is thus firstly formed which may be based on a material 215 having an intrinsic elastic stress, such as for example SiN, adapted to induce a mechanical stress in the substrate. Implantation of regions 10a of the support layer 10 is then carried out through openings of the mask 214. Then, the recrystallization annealing of the regions 10a of the support layer is carried out. The masking 121 is then removed, for example by etching with ortho-phosphoric acid when the masking is based on silicon nitride SiN. Next, a grid 32 is formed facing several zones 10a which have been rendered amorphous and then recrystallized.
    [0023] Source areas 41 and drain 42 can then be made (Figure 6). According to one possibility of implementing one or the other of the examples of processes which have just been described, the transistor T whose channel is constrained may be in FD-SOI technology (for "Fully Depleted" Silicon On Insulator) or UTBB (UTBB for "Ultra Thin Body and Box") that is to say with an ultra-thin insulating layer 11, in particular with a thickness between 5 nm and 25 nm just below an ultra channel. -thickness of thickness in particular between 3 nm and 25 nm and which is not doped. As a variant of one or the other of the examples which have just been given, the method according to the invention can advantageously be carried out on a semiconductor-on-insulator substrate whose surface layer is based on another semiconductor material. Si, for example a type III-V material.
    权利要求:
    Claims (12)
    [0001]
    REVENDICATIONS1. A method of producing a constrained channel transistor on a semiconductor-on-insulator substrate comprising a support layer, a surface semiconductor layer and an insulating layer separating the support layer and the surface semiconductor layer, the method comprising the steps of: a) forming a masking (14, 114, 214) on a first region (12a) of the surface semiconductor layer (12) in which a channel region of a transistor is to be performed, b) amorphous at least a first region (10b) of the support layer (10) located in line with an area of the superficial semiconductor layer that is not protected by masking, the first region adjoining a second region (10a) of the support layer (10) located in line with the masking, c) recrystallizing the first region (10b) of the support layer, during this recrystallization, a constraint canic being applied on the substrate by a stress layer (21, 214) deposited on the substrate, d) removing the masking and the stress layer: e) forming on the first zone (12a) of the surface layer, a grid ( 32) for the transistor.
    [0002]
    2. The method of claim 1, wherein the stress layer (21) is deposited after forming the masking (14, 114) and prior to recrystallization.
    [0003]
    3. The method of claim 1, wherein the masking (214) is based on a material (215) constrained, the masking forming the stress layer in step c) .30
    [0004]
    The method of one of claims 1 to 3, wherein the masking is formed of a plurality of distinct masking blocks (114, 214).
    [0005]
    5. Method according to one of claims 1 to 4, wherein the masking comprises one or more openings (116) unveiling the first zone (12a) in which the channel region of a transistor is intended to be realized.
    [0006]
    6. Method according to one of claims 1 to 5, wherein the masking comprises one or more openings between the masking blocks (114, 214), at least one opening (216) masking revealing a first zone (12b) of the surface layer, in which or on which a source or drain zone of the transistor is made or intended to be made.
    [0007]
    7. Method according to one of claims 4 to 6, wherein the masking blocks are elongated parallel blocks which extend in the direction of their length in a predetermined direction, this predetermined direction being provided orthogonal to a given axis ( B'B) passing through the first zone of the superficial layer, this axis being parallel to a direction in which a current is intended to flow in the first zone (12a) between a source zone and a drain zone of the transistor.
    [0008]
    8. The method of claim 7, wherein in step a), the surface layer is based on a constrained semiconductor material, the mechanical stress applied by the stress layer in step c) being a constraint. mechanical type opposite to that of this material.
    [0009]
    9. The method of claim 7 or 8, wherein in step a), the substrate is of sSiGe01 type ("strained Silicon Germanium On insulator") having a surface layer of SiGe constrained in bi-axial compression, the mechanical stress applied in step c) by the stress layer being a mechanical stress in tension.
    [0010]
    10. Method according to one of claims 1 to 7, wherein the thickness of the superficial semiconductor layer is less than 25 nm and the thickness of the insulating layer is less than 25 nm.
    [0011]
    11. Method according to one of claims 1 to 7, the surface layer is based on a III-V material.
    [0012]
    A transistor on a semiconductor-on-insulator substrate comprising a semiconductor material-based support layer, a surface semiconductor layer, and an insulating layer separating the support layer and the surface semiconductor layer. semiconductor material of the support layer comprising dislocations, the dislocations being arranged facing a channel region of the transistor.
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1456521A|FR3023411B1|2014-07-07|2014-07-07|LOCALIZED GENERATION OF STRESS IN A SOIL SUBSTRATE|FR1456521A| FR3023411B1|2014-07-07|2014-07-07|LOCALIZED GENERATION OF STRESS IN A SOIL SUBSTRATE|
    US14/791,713| US9502558B2|2014-07-07|2015-07-06|Local strain generation in an SOI substrate|
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